Core engineering and protocols for Cache-Timing Attack Mitigation.
In shared cloud environments, an adversary running in an adjacent virtual machine or container can monitor shared CPU cache lines (L3 cache). By executing Prime+Probe or Flush+Reload techniques, the attacker observes memory access patterns generated during ML-KEM polynomial transformations, reconstructing secret polynomial coefficients through memory access timing.
MLKEMSec eliminates secret-dependent memory indexing entirely. All twiddle factor arrays are pre-loaded into dedicated vector registers or arranged in continuous memory blocks that are accessed sequentially via vector instructions, ensuring that every cache line is accessed on every execution cycle with zero timing differential.